A high density vertical 3-transistor, 3-T, gain cell is realized for DRAM operation. The value in the memory cell can be accessed by reading it. Note: i) N1 >> N2 >> P1 ii) There are other explanations with the transistors named M1, M2 etc. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation. The memory cell is the fundamental building block of computer memory.The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Memory cells that use fewer than four transistors are possible – but, such 3T or 1T cells are DRAM, not SRAM (even the so-called 1T-SRAM). Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M 5 and M 6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. DRAM Cell Design. Single-transistor dynamic random access memory (DRAM) cells, created using the III–V compound semiconductor indium gallium arsenide, can be scaled down to a gate length of 14 nm. I have the basic Read and Write operation of a 6T SRAM Cell below with figures. Figure 1: DRAM Cell. A typical 3-transistor DRAM cell employs the use of access transistors and a storage transistor to switch the input capacitance of the storage transistor on (bit value 1) and off (bit value 0). Index Terms— Noise margin, read stability, read noise margin (RNM), cell Ratio, Pull up transistor, SRAM cell, Static The array of transistors are tied to read and write columnlines and rowlines that are also known as bitlines and wordlines respectively . For these reasons, DRAM is used to implement the bulk of main memory. Two separate word lines are connected to two transfer device gates to either write data or read data. driver transistors during read operation this paper analyzes the read stability and write ability of 6T, SRAM cell structures. Its value is maintained/stored until it is changed by the set/reset process. By packaging DRAM cells judiciously, DRAM memory can sustain large data rates. Two vertical transfer devices and, one on either side of the cell, serve to connect the cell to a shared data/bit line. A Dram cell consists of a capacitor connected by a pass transistor to the bit line (or digit line or column line). 3-transistor DRAM cell MP1, MP2- column precharge transistors PC pre charge signal M2 - storage device C1 Parasitic storage capacitance C2, C3 column capacitances M1, M3 - R/W access switches RS, WS - R/W control lines Data_in, Data_out - I/O lines ~DATA data input Precharge operation Every I think the naming convention followed in the material I referred (a lecture I found online) is good because…